interesting (?) ARM instructions

Reference CARD

Arm Infocenter

ℾ specifies the odd register of an even-odd pair for DoubleWords

WFE 20 BF Wait For Event clock stops until IRQ, FIQ, other processor signals
BIC[S] 85 43Bit Clear aka AND. if S cc is effected
SMULL[S] 85 43Multiply
ldrb byte ldrsb t=b
ldrh half lbrsh t=h
ldrd dbl t=d
Load with immediate offset,
pre-indexed immediate offset, or
post-indexed immediate offset.
ldr{t}{cond} Rt, {,#offset}] immediate
ldr{t}{cond} Rt,[Rn  ,#offset]! pre-indexed
ldr{t}{cond} Rt,[Rn] ,#offset] post-indexed

Rt target, Rn address base, ℾ Rt+1 ; address must be Word aligned

LDR     r8,[r10]      ; loads R8 from the address in R10.
LDRNE   r2,[r5,#16]!  ; (conditionally) loads R2 from a word
                      ; [R5]+16 bytes & increments R5 by 16.
i.e. if R5 pointed to the nth entry in a 16 byte table,
loads first word from next entry and advances R5 to next entry

if Rt is PC branches to the address loaded.

sub{S}{cond B0 Subtract without carry sub{S}{cond {Rd}, Rn, O2
Rd <- Rn - O2
S set Condition Code ; Rd destination, Rn original value; Thunb:imm 0..4096
UXTH[cc [Rd],Rm[,rotation] Zero extend Halfword.
Extends a 16-bit value to a 32-bit value.
rotation ROR #8|16|24
CBZ r,label Compare and Branch on Zero. aka CMP;
BEQ but CC not affected.
IT cc If Then
Following instruction executed without effecting CC
IT cc when c is Then or Else ex ITTE
 ADDEQ r0, r1, r2

Condition Codes cc

suffixes used on instructions

EQ EQual
NE Not Equal
CS Carry Set == HS
HS Unsigned Higher or Same == CS
CC Carry Clear == LO
LO unsigned LOwer == CC
MI MInus or negative result
PL Positive or zero result
VS oVerflow Set
VC oVerflow Clear
HI unsigned HIgher
LS unsigned Lower or Same
GE signed Greater than or Equal
LT signed Less Than
GT signed Greater Than
LE signed Less than or Equal
AL ALways (default)

flag bits

N Negative
Z Zero
C Carry
V oVerflow
Q DSP overflow

Additional Flags

T Thumb
ICIH interrupt continuable
ISR Interrupt Service Routing number


Call with BL , return using BX LR
Use R0..2 to pass args to subroutines
use R0 for result

ARM assembler Direcives

A GCC optimizatins include: