Segger J-Link Commander debugger

Segger web page wiki 6/17/21 firefox says last-updated May 27, 2021

The complete manualis located at the Segger web page: J-Link

A wiki is at wiki.Segger.com/J-Link_Command_Strings

These notes based on version 6.87b 11/13/20

/Applications/SEGGER/JLink/JLinkExe \

  -Device NRF52832_XXAA -Autoconnect 1 -if SWD -Speed 4000 

-CommandFile  j-link.cmd

Sample startup

To show output from NRF_LOG_…,
in another window start:

/Applications/SEGGER/JLink/JLinkRTTClient

which will wait for connection to J-Link

or
telnet localhost 19021
(permits entering commands for NRF_LOG_BACKEND_FLASH_CLI_CMDS)

-AutoConnect  [0|1]

-Device example :NRF52832_XXAA

-If JTAG | SWD

-Speed Freq|auto|adaptive Default 4000kHz

-CommanderScript,

               -CommandFile

-JLinkScriptFile special connection sequence before communication with the core

-USB serialNumber

-SettingsFile file

-IP addr Example -IP 192.168.1.17

-RTTTelnetPort port

-ExitOnError

-SelectEmuBySN

-JTAGConf  IRPre|DRPre example: -JTAGConf 4,1

-Log  file

Connect via USB.

connect [ usb [ 0 | 1 | 2 | 3 ] ]

Asks for DEVICE (suggests last used, ex NRF52832_XXAA)
target interface (like SWD)

Mode-Of-Entry, i.e.
Reason CPU halted

moe

CPU halted because DBGRQ was asserted.          CPU halted due to vector catch.

halt | go

 h | g 
NumSteps 
  [0̸|1]

Simulate NumSteps 0̸ Do not start if a BreakPoint is within NumSteps 1: Overstep BPs
After halt, WatchDog timer WILL expire during halt and WDOG_HANDLER will be invoked after entering g

halt

PC = 00000000, CycleCnt = 00000001
R0 = EFBFEB40, R1 = 00007FFE, R2 = 6D09E1BD, R3 = 00007FFF
R4 = 00000005, R5 = 00000000, R6 = 00000005, R7 = 00000000
R8 = 00446E80, R9 = 00000001, R10= 00446E80, R11= 00000001
R12= EFBFEB60
SP(R13)= 00007FFE, MSP= 6D09D4C7, PSP= 00007FFF, R14(LR) = 00000004
XPSR = 00000005: APSR = nzcvq, EPSR = EFBFEB90, IPSR = 01E (INTISR15)
CFBP = 6CF9E5B9, CONTROL = 00, FAULTMASK = 40, BASEPRI = 00, PRIMASK = 505AB0

FPS0 = EFBFEB40, FPS1 = 00007FFE, FPS2 = 6D09E1BD, FPS3 = 00007FFF
FPS4 = 00000005, FPS5 = 00000000, FPS6 = 00000005, FPS7 = 00000000
FPS8 = 00446E80, FPS9 = 00000001, FPS10= 00446E80, FPS11= 00000001
FPS12= EFBFEB60, FPS13= 00007FFE, FPS14= 6D09D4C7, FPS15= 00007FFF
FPS16= 00000004, FPS17= 00000000, FPS18= 00000005, FPS19= 00000000
FPS20= EFBFEB90, FPS21= 00007FFE, FPS22= 6CF9E5B9, FPS23= 00007FFF
FPS24= 00400CC0, FPS25= 00000001, FPS26= 00505AB0, FPS27= 00000001
FPS28= EFBFED40, FPS29= 00007FFE, FPS30= 00446E80, FPS31= 00000001
FPSCR= EFBFEBC0


WARNING: CPU could not be halted

Perhaps device is not connected or powered.

Set Program Counter SetPC EVENAddr

Registers

rreg i | regname

 regs  J-Link>regs
PC = 00078422, CycleCnt = 00000061
R0 = 00078485, R1 = 00000007, R2 = 00000000, R3 = F0000FE8
R4 = 00000FFC, R5 = 0007E080, R6 = 10001000, R7 = 0007E000
R8 = 00000000, R9 = 00000000, R10= 00000000, R11= 00000000
R12= 00000000
SP(R13)= 2000FFF8, MSP= 2000FFF8, PSP= 00000000, R14(LR) = 0007848B  (R15 is PC)
XPSR = 41000000: APSR = nZcvq, EPSR = 01000000, IPSR = 000 (NoException)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00

FPS0 = 00000000, FPS1 = 00000000, FPS2 = 00000000, FPS3 = 00000000
…
FPS28= 00000000, FPS29= 00000000, FPS30= 00000000, FPS31= 00000000
FPSCR= 00000000

 0 R0 
 1 R1 
 2 R2 
…
12 R12
13 R13 (SP)^†
14 R14 
15 R15 (PC)^†

ARM docs

 16 XPSR  APSR, IPSR, and EPSR
 17 MSP  MainStackPointer 
 18 PSP  ProcessStackPointer
 19 RAZ 
 20 CFBP 
 21 APSR 
 22 EPSR 
 23 IPSR

 24 PRIMASK 
 25 BASEPRI 
 26 FAULTMASK 
 27 CONTROL 
 28 BASEPRI_MAX 
 29 IAPSR 
 30 EAPSR 
 31 IEPSR 
 32 FPSCR

 33 FPS0 
 34 FPS1 
 39 FPS6 
…
 44 FPS11 
…
 50 FPS17 
…
 60 FPS27

Non-Secure

 70 MSPLIM_S 
 71 PSPLIM_S 
 72 MSPLIM_NS 

 77 BASEPRI_NS 
 78 FAULTMASK_NS 
 79 CONTROL_NS

 80 BASEPRI_MAX_NS 
 81 PRIMASK_S 
 82 BASEPRI_S 
 83 FAULTMASK_S 
 84 CONTROL_S 
 85 BASEPRI_MAX_S 
 86 MSPLIM 
 87 PSPLIM

Write register.

wreg RegName, Value. For PC use SetPC. For SP use MSP

wreg R9,0xD66
reg 9 
R9 = 0x00000D66

read memory
write memory

layout

When writing to flash
j-Link MAY cache the writes.
When reading the cache is queried
This causes the application and other debuggers, for example nrfjprog, to continue to see the original contents of the flash.

This behavior can be changed using:

exec SetEnableMemCache = 0

See ProjectFile

exec SetAllowStopMode 1 ???

mem[8|16|32|64][Zone:]Addr[,ngroups(in hex)  
w1|w2|w4|w4 [Zone:]Addr[ xData …]

Zone Name of memory zone to access.

w4 10001080 FFFF541C (looks like SHTC) FLASH:Change 1 to 0 OK , 0 to 1 needes erase(J-Link does that!) mem32 10001080 4 10001080 = FFFF541C FFFFFFFF FFFFFFFF FFFFFFFF w4 10001080 01020304 mem32 10001080 1 10001080 = 01020304 mem 10001080 4 10001080 = 04 03 02 01 gawk! mem16 10001080 2 10001080 = 0304 0102 (int16s) mem 48760,10 with text 00048760 = 6D 61 69 6E 20 63 61 6C 6C 69 6E 67 20 74 65 73 main calling tes mem8 48760,10 no text 00048760 = 6D 61 69 6E 20 63 61 6C 6C 69 6E 67 20 74 65 73

mem 10001080 4 10001080 = FF FF FF FF w1 10001083 FE Writing FE -> 10001083 mem 10001080 4 10001080 = FF FF FF FE mem32 10001080 1 10001080 = FEFFFFFF it only looks bad w4 10001081 0A0B0C0D Writing 0A0B0C0D -> 10001081 Mis-aligned memory write: Address: 0x10001081, NumBytes: 4, Alignment: 4 (Word-aligned) mem32 10001080 2 10001080 = 0B0C0DFF FFFFFF0A mem 10001080 8 10001080 = FF 0D 0C 0B 0A FF FF FF mem8 10001080 8 10001080 = 03 0D 0C 0B 0A FF FF FF

Get the address of a static global from the map.

 grep -A1 vbat *.map |\
         sed "s/0x00000000\(........\)/mem16 \1,1/; s/        0x2//"
 .bss.vbat      mem16 20004486,1 _build/ruuvi_firmware_main.c.o

mem16 20004486,1
20004486 = ADC

Use: echo 'ibase=16;ADC' |bc to see 2780 millivolts)

mem32 1f000,40 Interrupt Service Routine table


0001F000 = 20010000 0003172D 00031755 00031757 
0001F010 = 00031759 0003175B 0003175D 00000000 
0001F020 = 00000000 00000000 00000000 0003175F 
0001F030 = 00031761 00000000 00031763 00031765 
0001F040 = 0002B451 00031767 00031767 0002BFD5 
0001F050 = 00031767 00031101 0002B889 0002C3E5 
0001F060 = 0002C06D 0002C135 0002C1FD 00031767 
0001F070 = 00031767 0002BB51 00031767 00031767 
0001F080 = 00023E95 00030005 00031767 00031767 
0001F090 = 000300C9 00031767 0003165D 00031767 
0001F0A0 = 00031767 00031767 0002C2C5 00030E45 
0001F0B0 = 00031767 00031767 00000000 00000000 
0001F0C0 = 00031767 00031767 00031767 00031767 
0001F0D0 = 0002BC2D 00031767 00031767 00000000 
0001F0E0 = 00000000 00000000 00000000 00000000 
0001F0F0 = 00000000 00000000 00000000 00000000 

mem64 2000,4  (4 64bit quad(?)words) 
00002000 = D0032D1278A5BBBC E7B8DFFFD0042D13 
00002010 = F7FFE001FF6FF7FF F006D1B12800FF55

w4 10001080 00010203 04050607 NRF_UICR->CUSTOMER

Writing 00010203 -> 10001080
Writing 04050607 -> 10001084

mem32 10001080,20 
10001080 = 00010203 04050607 FFFF0908 FFFFFFFF 
10001090 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
…
100010FF = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

Fill stack (where local dynamic variables are allocated) with C0FFEE:

w4 2000FC00 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FC40 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FC80 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FCC0 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FD00 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FD40 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FD80 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FDC0 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FE00 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FE40 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FE80 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FEC0 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FF00 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FF40 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FF80 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE
w4 2000FFC0 C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE C0FFEE

Stack is used for local variables. There's not much point in filling the top (i.e. FFFF )

Display stack:
mem32 2000FC00,100 or less mem32 2000FF00,40

2000FF00 = 3A50D29F 00961AFE 00001903 0A040A02 
2000FF10 = 75755209 61316976 00003639 00000000 
2000FF20 = 00000006 00021E03 20002D9C 00000000 
2000FF30 = 20002DAC 00000AF3 00000060 A801BE00 
2000FF40 = 00000001 80000000 00000000 FFFFFFF9 
2000FF50 = 00000614 21000018 01000001 40020518 
2000FF60 = 00000001 80000000 00000000 00012639 
2000FF70 = 0001263A 21000000 50000000 00020000 
2000FF80 = 00080000 00003AFE 000000FE 000011DF 
2000FF90 = 000242D1 0000001F 00000001 80000000 
2000FFA0 = 50000000 00023727 00000021 00000039 
2000FFB0 = 0000001A 00000096 8485C80E 2E3BBCEA 
2000FFC0 = 12222139 12222139 00000FF8 00000002 
2000FFD0 = 00000005 00000009 20002E0C 00000000 
2000FFE0 = 00000000 20003B68 00000000 00000000 
2000FFF0 = 00000000 20000000 00000000 0001F4AB

Spill some COFFEE into flash too.

J-Link> w4 00065000 C0FFEE C0FFEE C0FFEE C0FFEE 
Writing 00C0FFEE -> 00065000
J-Link>mem32 00065000 4
00065000 = 00C0FFEE 00C0FFEE 00C0FFEE 00C0FFEE 
J-Link>q
J-Link: Flash download: Bank 0 @ 0x00000000: 1 range affected (4096 bytes)
J-Link: Flash download: Total: 0.340s (Prepare: 0.183s, Compare: 0.099s, Erase: 0.006s, 
        Program & Verify: 0.040s, Restore: 0.011s)
J-Link: Flash download: Program & Verify speed: 100 KB/s

Data RAM System	Code RAM
`2000 F000`	0800 FFFF
`mem 20000000,800`	0800 0000
80..FC customer mem 10001080,80 UICR 10000000 FICR: 14..7C Nordic Firmware NRFFW[0..11] 8 0000 .. 80 ffff, code ram 0000 .. 7 FFFF, flash FICR->DEVICEID not MAC mem 10000060,8 10000060 = 1A 04 D7 6E 04 BA FA D1 FICR->DEVICEADDRTYPE FE public, FF random mem 100000a0,4 FICR->DEVICEADDR mem 100000a4,6 displayed as MAC 1A 1E 4A 74 FA 37 ; F7:FA:74:4A:1E:1A 03 AD 43 C6 C0 B2 ; F2:C0:C6:43:AD:03 0E 23 6C 9C 8B 14 ; D4:8B:9C:6C:23:0E BC 20 DD 3F 38 A9 ; E9:38:3F:DD:20:BC

Load data file

loadfile filename. 
hex |  mot | bin | rec  [,addr]  for bin

Halts the CPU then loads the file.
After the load completes, a reset MUST be issued manually to set the PC to the Start Address.

loadfile test_v3.28.13_full.hex
Downloading file [test_v3.28.13_full.hex]...
Comparing flash   [100%] Done.
Erasing flash     [100%] Done.
Programming flash [100%] Done.
Verifying flash   [100%] Done.
J-Link: Flash download: Bank 0 @ 0x00000000: 3 ranges affected (319488 bytes)   

J-Link: Flash download: Total time needed: 5.759s 
       (Prepare: 0.119s, 
        Compare: 0.045s, Erase: 0.000s, Program: 5.492s, Verify: 0.015s, Restore: 0.086s)
O.K.

A reset command must be issued before go.

File is of unknown / supported format.
The file extension should be .hex or

Failed to open file.
File cannot be read or the file may have a checksum error or other format problem.

[TAB][TAB] lists the current directory.

a[TAB] lists all files and directories beginning with a ( as with name completion.)

d[TAB] completes the directory name beginning with d.
Replacing the trailing space with a /[TAB] lists all files and directories under dir.

../[TAB] lists items in the parent directory.

Reset

r[x DelayAfterReset ]
sets ALL regs=0,
Then starts bootloader setting up SP and PC
This does NOT causes the static variables to be initalized which WILL be initalized before main is entered.
SetBP aaaaa (main) then g.
When break point is hit static variables have been initalized and can be viewed or changed.

Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
J-Link>regs
PC = 00000A80, CycleCnt = 00000000

If PC = FFFFFFFE there probably isn't an image loaded (with a valid start address)!

reset types

Erase

erase [Saddr,Eaddr] i.e. set flash to x'FFFFFFFF'

 erase 0 65000 # up to bottom on start_storage_flash on nRF52832.
Erasing selected range...
J-Link: Flash download: Total time needed: 0.598s 
        (Prepare: 0.178s, Compare: 0.000s, Erase: 0.285s, Program: 0.000s, Verify: 0.000s, Restore: 0.134s)
J-Link: Flash download: 
Flash sectors within Range [0x00000000 - 0x00065000] deleted.
Erasing done.

Without Saddr,Eaddr performs erase chip including NRF_UICR->CUSTOMER

erase
Without any give address range, Erase Chip will be executed
Erasing device...
J-Link: Flash download: Total time needed: 0.341s 
    (Prepare: 0.178s, Compare: 0.000s, Erase: 0.026s, Program: 0.000s, Verify: 0.000s, Restore: 0.135s)
Erasing done.

J-Link> mem32 10001080,4    // CUSTOMER
00000000 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
J-Link> mem32 7FFE0,8       // top of FLASH
0007FFE0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
0007FFF0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 

00800000 = 00000000 00000000 00000000 00000000  Code RAM begins??
00800010 = 00000000 00000000 00000000 00000000

Save memory

layout

see nrfjprog --readuicr file.hex--readcode , --readram

savebin filename, addr, NumBytes
in mem format i.e. 03 02 01 00 07 06 05 04
where mem32 shows 00010203 04050607

> savebin 1a96hungRAM.bin 20000000 0xFFFF

Opening binary file for writing... [1a96hungRAM.bin]
Reading ... bytes from addr 0x20000000 into file...O.K.

> /usr/bin/hexdump -C 1a96hungRAM.bin > 1a96hungRAM.txt

> savebin FICRUICR.bin 10001000 0x100  bytes
 
Opening binary file for writing... [FICRUICR.bin]
Reading 256 bytes from addr 0x10001000 into file...O.K.

> /usr/bin/hexdump  -e  '"%07 _ax" 4/4 " %08X" "\n"' FICRUICR.bin   
# format with 7 digits of address, 4 groups of 4 bytes per group 8digit HEX end each set with nl.

savebin FlashDataStorage.bin  65000 15000

Load *.bin file loadbin filename.bin, addr

Verfy binary in memory verifybin filename, addr

Single step

s [NumSteps (dec)] Instruction displayed has already been executed!
WatchDog timer WILL expire during step and WDOG_HANDLER will be invoked after entering g


J-Link>s
00024AFC:  4F F6 FF 72        MOVW      R2, #0xFFFF
J-Link>s 3
000784AC:   7A 4A              LDR       R2, [PC, #+0x1E8]
000784AE:   1B 68              LDR       R3, [R3]
000784B0:   C3 F3 42 33        UBFX      R3, R3, #13, #3

J-Link>regs
PC = 00024B00, CycleCnt = 014A8587
R0 = 00000000, R1 = 00000000, R2 = 0000FFFF, R3 = 00000000 …

0001F832:  01 38              SUBS      R0, #1
J-Link>s
0001F834:  C3 D1              BNE       #-0x7A
J-Link>s
000008E4:  06 4B              LDR       R3, [PC, #+0x18]
…
0000031C:  4F F0 10 24        MOV       R4, #0x10001000     Config area
00000320:  A0 69              LDR       R0, [R4, #+0x18]
00000322:  40 1C              ADDS      R0, R0, #1
00000324:  05 D0              BEQ       #+0x0A
00000326:  A5 69              LDR       R5, [R4, #+0x18]
00000328:  A6 69              LDR       R6, [R4, #+0x18]
0000032A:  80 35              ADDS      R5, #128
0000032C:  30 79              LDRB      R0, [R6, #+0x04]
0000032E:  AA 28              CMP       R0, #170
00000330:  08 D0              BEQ       #+0x10
00000332:  60 69              LDR       R0, [R4, #+0x14]
00000334:  40 1C              ADDS      R0, R0, #1
00000336:  2D D0              BEQ       #+0x5A
00000338:  60 69              LDR       R0, [R4, #+0x14]
0000033A:  00 68              LDR       R0, [R0]
0000033C:  40 1C              ADDS      R0, R0, #1
0000033E:  29 D0              BEQ       #+0x52
00000340:  60 69              LDR       R0, [R4, #+0x14]
00000342:  2C E0              B         #+0x58

0000039E:  00 F0 A3 FA        BL        #+0x546

000008E8:  06 4A              LDR       R2, [PC, #+0x18]
000008EA:  10 60              STR       R0, [R2]
000008EC:  01 68              LDR       R1, [R0]
000008EE:  81 F3 08 88        MSR       MSP, R1
000008F2:  40 68              LDR       R0, [R0, #+0x04]
000008F4:  00 47              BX        R0



00009A9E:  20 BF              WFE  
00009AA0:  D4 F8 04 01        LDR       R0, [R4, #+0x104]
00009AA4:  00 28              CMP       R0, #0
00009AA6:  FA D0              BEQ       #-0x0C

00009A9E:  20 BF              WFE  
00009AA0:  D4 F8 04 01        LDR       R0, [R4, #+0x104]
00009AA4:  00 28              CMP       R0, #0

00079E18:  06 49              LDR       R1, [PC, #+0x18]
00079E1A:  07 4A              LDR       R2, [PC, #+0x1C]

DisAssemble

disassemble [addr] CPU must be halted.
no abbreviation
Caution: using an arbitrary addr Will produce incorret results if not an initial instruction boundry.

disassemble 416
00000416:   40 F6 FC 74        MOVW      R4, #0xFFC
0000041A:   20 68              LDR       R0, [R4]
0000041C:   4F F0 10 26        MOV       R6, #0x10001000
00000420:   40 1C              ADDS      R0, R0, #1
00000422:   23 D0              BEQ       #+0x46
00000424:   20 68              LDR       R0, [R4]
00000426:   40 1C              ADDS      R0, R0, #1
00000428:   0C D0              BEQ       #+0x18
0000042A:   20 68              LDR       R0, [R4]
0000042C:   40 1C              ADDS      R0, R0, #1

instruction BreakPoint

SetBP aaaaa [A|T] [S|H]
ARM mode: 2xxxx | Thumb mode: 0xAB Soft|hard

ClrBP handleID

Example:
Use grep to find startup.main from the LoaD map

grep -A1 .text.main   *.map 
 .text.startup.main
                0x000000000357f8      0x518 _build/ruuvi_firmware_main.c.o

Call to ri_log(levl,msg)

LDR    R1,  [PC, #+28]  / string 
MOVS   R0, #3    level ?
BL     #-50D0     ri_log   002f4f8 

PUSH  {R3,LR}  LR/ 
CBZ   R1, #+A
MOV   r2, R1     / string
LDR   R3, [PC, #+30]  / 03
LDRB  R3, [R3]
CMP   R3, R0
BHI   #+10
POP   {r3,PC}
BL    #+1B8

  
PUSH  {R3,LR}
BL    #-7A

PUSH  {R3,LR}
LDR   R1, [PC, #+3C]
LDR   R0, [PC, #+3C]
BL     #-2FFA


PUSH   {R4-R5,LR}
SUB    SP, SP, #20   open up stack

setBP 24aec 
Breakpoint set @ addr 0x00024AEC (Handle = 5)

When breakpoint is encountered a simple J-Link> prompt is presented.
Use moe to determine what happened.

     CPU halted due to code breakpoint match.

s executes next instruction.

Display breakpoints (i.e. FPB :(?)

 mem32 E0002000,10
E0002000 = 00000261 20000000 4003454D 4002F4F9 
E0002010 = 40034589 00000000 00000000 00000000

ARM instructions

Set the reset type.

RSetType type Affects core & peripherals unless noted. See j-Link section 7.9.2 (Ruuvi / nRF52832 is Cortes-M4)

`RSetType 0`	Normal	via `VC_CORERESET` and `SYSRESETREQ.` initial setting. Make sure that the device halts immediately after reset (before it can execute any instruction of the application) by setting the VC_CORERESET in the DEMCR. Reset the core and peripherals by setting the SYSRESETREQ bit in the AIRCR. Wait for the S_RESET_ST bit in the DHCSR to first become high(resetactive)and then low (reset no longer active) afterwards. ClearVC_CORERESET
`RSetType 2`	ResetPin	using RESET pin. CPU does not start execution. J-Link> RSetType 2 Reset type RESETPIN: Resets core & peripherals using RESET pin. J-Link>r Reset delay: 0 ms Reset type RESETPIN: Resets core & peripherals using RESET pin. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via reset pin Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?). Reset: Reconnecting and manually halting CPU. Found SW-DP with ID 0x2BA01477 DPIDR: 0x2BA01477 AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) Found Cortex-M4 r0p1, Little endian. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.VECTRESET.
`RSetType 3`	Connect under Reset	connect to target keeping RESETactive.
`RSetType 5`	Halt Before BTL	as with `8` halts CPU before the bootloader.
`6`	Kinetis	via strategy NORMAL. Watchdog disabled after reset
`7`	ADI^† Halt after kernel	halts CPU after the ADI kernel. J-Link>RSetType 7 Reset type ADI HALT AFTER KERNEL: Resets core & peripherals, halts CPU after the ADI kernel. J-Link>r Reset delay: 0 ms Reset type ADI HALT AFTER KERNEL: Resets core & peripherals, halts CPU after the ADI kernel. Core did not halt after reset, manually halting CPU... J-Link>moe CPU halted because DBGRQ was asserted. J-Link>regs PC = 00000A80, CycleCnt = 00000000
`8`	Core and Peripherals	via SYSRESETREQ bit only.
`1`	Core	not recommended. Core only ( via VECTRESET bit, CPU does not start execution)
`9`	LPC1200	via strategy normal. Watchdog disabled after reset
`10`	S3FN60D	via strategy normal. Watchdog disabled after reset
`11`	LPC11A	Performs some special handling which is needed by some LPC11A bootloaders.

data WatchPoint

SetWP|ClrWP Addr [R|W] [Data [D-Mask] [A-Mask]]

SetWP 20002da2
Watchpoint set @ addr 0x20002DA2 (Handle = 0x00000004)

When breakpoint is encountered a simple J-Link> prompt is presented.
Use moe to determine what happened.

moe
     CPU halted due to data breakpoint unit 3 match

Wait until CPU halts or
timeout exceeded. WaitHalt TimeoutMs Default 1000

Wait Sleep ms

hardware status

st

VTref=3.300V
ITarget=0mA
TCK=0 TDI=1 TDO=1 TMS=1 TRES=1 TRST=1
Supported target interface speeds:
- 10 MHz/n, (n=10). = 1000kHz, 909kHz, 833kHz, ...

hardware info

hwinfo /

HWInfo[00] = Target power is disabled
HWInfo[02] = 0mA	(ITarget)
HWInfo[03] = 0mA	(ITargetPeak)
HWInfo[04] = 0mA	(ITargetPeakOperation)
HWInfo[10] = 0ms	(ITargetMaxTime0)
HWInfo[11] = 0ms	(ITargetMaxTime1)
HWInfo[12] = 0ms	(ITargetMaxTime2)
HWInfo[13] = 0000000

Write vector catch. VCatch Value

Unlock a device.

unlock DeviceName

list of supported device names.

LM3Sxxx [Auto]
Kinetis
EFM32Gxxx
LPC5460x 
           nRESET has to be connected

Test command to visualize printf output from the target device, term using DCC (SEGGER DCC handler running on target)

CoreSight register

  ReadAP     

ReadDP

 J-Link>readap 2
Reading AP register 1 = 0x20002007 (0 read repetitions needed)
J-Link>readap 2
Reading AP register 2 = 0x00000000 (0 read repetitions needed)
J-Link>readap 3
Reading AP register 3 = 0xA044E7D5 (0 read repetitions needed)
J-Link>readap 4
Reading AP register 4 = 0x23000052 (0 read repetitions needed)
J-Link>readap 5
Reading AP register 5 = 0x20006000 (0 read repetitions needed)
J-Link>readap 6
Reading AP register 6 = 0x00000000 (0 read repetitions needed)
J-Link>readap 7
Reading AP register 7 = 0xF203BEDA (0 read repetitions needed)
J-Link>readap 8
Reading AP register 8 = 0x23000052 (0 read repetitions needed)
J-Link>readap 9
Reading AP register 9 = 0x20003000 (0 read repetitions needed)

J-Link>readap 1
Reading AP register 1 = 0x20002000 (0 read repetitions needed)
J-Link>readap 1
Reading AP register 1 = 0x20004000 (0 read repetitions needed)
J-Link>readap 1
Reading AP register 1 = 0x20002000 (0 read repetitions needed)
J-Link>readap 1
Reading AP register 1 = 0x20000000 (0 read repetitions needed)
J-Link>readap 1
Reading AP register 1 = 0x20006000 (0 read repetitions needed)
J-Link>readap 1
Reading AP register 1 = 0x20004000 (0 read repetitions needed)
J-Link>readap 1
Reading AP register 1 = 0x20002007 (0 read repetitions needed)
J-Link>readap 1
Reading AP register 1 = 0x20005000 (0 read repetitions needed)

First read returns the data of the previous read. An additional read of DP reg 3 is necessary to get the data.
For SWD, data is returned immediately.
For JTAG the data of the previous read is returned. An additional read of DP reg 3 is necessary to get the data.

WriteAP WriteDP

CoreSight register via SWD.

SWDReadDP

J-Link>SWDReadDP 1
Read DP register 1 = 0xF0000040
J-Link>SWDReadDP 2
Read DP register 2 = 0xE000ED34
Read DP register 3 = 0xE000ED34
Read DP register 4 = 0xE000ED34
Read DP register 5 = 0x23000052
Read DP register 6 = 0xE000ED34

SWDReadAPM
First read returns the data of the previous read.
An additional read of DP reg 3 is necessary to get the data. Note: Correct data is returned immediately.

SWDWriteAP 
 SWDWriteDP

Export device names from the DLL internal device list

ExpDevList[XML] Filename

Opening text file for writing... [DLL-list]

DLLs

…

"Nordic Semi", "nRF52832_xxAA", "Cortex-M4", { {0x00000000, 0x00080000}, {0x10001000, 0x00001000} }, {0x20000000, 0x00010000}
"Nordic Semi", "nRF52832_xxAB", "Cortex-M4", { {0x00000000, 0x00040000}, {0x10001000, 0x00001000} }, {0x20000000, 0x00008000}
"Nordic Semi", "nRF52840_xxAA", "Cortex-M4", { {0x00000000, 0x00100000}, {0x10001000, 0x00001000} }, {0x20000000, 0x00040000}
"Nordic Semi", "nRF9160", "Cortex-M33", {0x00000000, 0x00100000}, {0x20000000, 0x00040000}

power trace

PowerTrace LogFile

        [ChannelMask RefCountSel]
        LogFile: File to store power trace data to
        ChannelMask: 32-bit mask to specify what channels shall be enabled
        SampleFreq: Sampling frequency in Hz (0 == max)
        RefCountSel:       0: No reference count

1: Number of bytes transmitted on SWO

ERROR: POWERTRACE is not supported by connected J-Link.

Measure length of scan chain. ms Scan chain

Identify length of scan chain select register

is

JTAG scan length: 0

Measure RTCK react time. mr

Write test words. wm NumWords

CP15

Read |Write CP15 rce | wce Op1, CRn, CRm, Op2 [, data

ICE

state of the embedded ice macrocell (ICE breaker) Ice

Read | write Ice reg. ri | wi RegIndex [, Data(hex)]

Trace

TClear

TStart | TStop

Trace could not be started, no trace clock.

TSetSize sizeX

Trace Buffer has been set to 0x0 Bytes (0kBytes)

TSetFormat 4|8|8

Regions (and analyze trace buffer)

TSR

Trace buffer size: 0KB (0KB Min, 0KB Max)
Trace format not selected.
0 Samples in 0 region(s)

File I/O

Read|Write file to emulator fread|fwrite

Read and display file from emulator fshow FileName [Offset [NumBytes]]

Delete file on emulator fdelete FileName

Display size of file on emulator fsize FileName

List directory on emulator

flist

This File I/O command is not supported by the connected probe

SecureArea Creates/Removes secure area on probe

Test

Run go/halt 1000 times

TestHaltGo

  ................................
Completed. 8420ms required

Run step 1000 times

TestStep

TestStep
Test single stepJ-Link: Flash download: Bank 0 @ 0x00000000: 1 range affected (65536 bytes)
J-Link: Flash download: Total: 1.563s 
    (Prepare: 0.182s, Compare: 0.089s, Erase: 0.045s, Program & Verify: 1.236s, Restore: 0.008s)
J-Link: Flash download: Program & Verify speed: 52 KB/s
....................................................................................................
Completed. 1630ms required

second run

Completed. 53ms required

Measure CPU speed.

TestCSpeed    
    [RAMAddr]

TestCSpeed 20000100
Testing CPU clock frequency @ address 0x20000100...
CPU running at 63806 kHz

Measure download speed into target memory.

TestWSpeed [Addr [Size]]

Speed test: Writing 8 * 64kb into memory @ address 0x00000000 ........
64 kByte written in 0ms ! (524288 KByte/sec)

Measure upload speed from target memory. TestRSpeed : [Addr [Size] [NumBlocks]]

Measure network speed: download(write)/up(read)

TestNWSpeed: [NumBytes [NumReps]]


 TestNRSpeed: [NumBytes [NumReps]]

 Using defaults 
Transferring 32768 KBytes (512 * 64 KBytes)
................................................................
12638.20 KBytes/sec     (aka 12 MB/s)
192 Blocks/sec
--again--
Using defaults 
Transferring 32768 KBytes (512 * 64 KBytes)
................................................................
13888.42 KBytes/sec     (aka 13 MB/s)
211 Blocks/sec

JTAG

Set number of IR/DR bits before ARM device. Config IRpre, DRpre

Set interface speed. speed freq|auto|adaptive, e.g. speed 2000, speed a

Read JTAG Id (Host CPU)

i

 JTAG Id: 0x2BA01477  Version: 0x2 Part no: 0xba01 Man. Id: 023B

Write JTAG command (IR). wjc xData

Write JTAG data (DR). wjd xData64, NumBits(dec)

Write Raw JTAG data. wjraw NumBits(dec), tms, tdi

RTAP Reset TAP Controller using state machine (111110)

Reset TA0P Controller (nTRST) rt

JTAG-Hardware

Create clock with
TDI = TMS = 0m c00

Clock ====== see 16.1.1

c

Data: 1

TCK Clear | set tck0|tck1 test clock input provides the clock for the test logic.

TDI clear | set 0|1 (really) Serial test instructions and data are received by the test logic at test data input

TMS clear | set t0 | t1 signal received at test mode select is decoded by the TAP controller to control test operations.

TRST clear | set trst0 | trst1 Test Data Output is the serial output for test instructions and data from the test logic.

RESET clear | set r0 |r1 (sic?

Connection

Connect ARM Pro or J-Link TCP/IP Server via TCP/IP.

ip ip_addr

 
Connecting to J-Link via IP...
FAILED: Can not connect to J-Link via TCP/IP (192.168.1.1, port 19020)

Show/Assign IP address and subnetmask of/to the connected J-Link.

ipaddr

Disconnecting from J-Link...O.K.
Disconnecting from J-Link...O.K.
Connecting to J-Link via IP...FAILED: Can not connect to J-Link via TCP/IP. No emulator found.

Show/Assign network gateway . gwaddr

Show/Assign network DNS server . dnsaddr

Configuration

Switch power supply for target.

power on|off [perm]

The connected debug probe does not support this command.

Read/Write configuration byte

rconf|wconf offset [, data]

rconf 0,80
Total size of config area: 0x100 bytes

00000000 = 00 01 FF FF FF FF FF FF FF FF FF FF FF FF FF FF 
00000010 = FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 
00000020 = FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 
00000030 = FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 
00000040 = FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 
00000050 = 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 
00000060 = FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 
00000070 = FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

Configuration of the connected J-Link.

[show]conf

USB-Address: 0
Enum. type:  Real-SN is used
KS-Power:    Off (Default)

SWO Single Wire Output

supported speeds

SWOSpeed

Supported speeds:
 - 12000 kHz/n, (n>=1). => 12000kHz, 6000kHz, 4000kHz, ...

SWOStart| SWOStop

Display SWO status

SWOStat after logging but not displayed vi RTviewerclient1,

MAIN:INFO:LEDs init

 J-Link>SWOStat
0 bytes in host buffer

However SWOread showed data and SWOstat

Read and display SWO data

SWORead


SWOStat
0 bytes in host buffer
J-Link>SWORead
256 bytes read (0 bytes in host buffer)
00000000 = 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 90 
00000010 = 37 00 00 00 A3 59 00 8B 70 A0 16 0C 01 00 00 00 
00000020 = 50 62 59 54 FF 7F 00 00 02 00 00 00 00 00 07 00 
00000030 = 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 90 
00000040 = 4F 00 00 00 00 00 00 00 10 00 10 00 10 00 00 00 
00000050 = 00 00 00 00 00 00 00 00 00 00 00 2C 06 00 16 00 16 00 21 see SWOshow PC
00000060 = 21 00 00 00 40 00 00 00 41 00 00 00 42 00 00 00 
00000070 = 43 00 00 00 44 00 00 00 45 00 00 00 46 00 00 00 
…
000000F0 = 4F 00 00 00 50 00 00 00 51 00 00 00 52 00 00 00

Read and analyze SWO data

SWOShow

J-Link>SWOShow
256 bytes read (0 bytes in host buffer)
Offset     Data               Meaning
-----------------------------------------------
001E-0020  16 00 21           PC = 0x00002100
0024-0024  40                 Timestamp sync. ITM/DWT (4)
0028-0029  41 00              SWIT(8): 00
002C-002E  42 00 16           SWIT(8): 00 16
0034-0035  01 00              SWIT(0): 00
0038-003A  02 00 00           SWIT(0): 00 00
003C-0040  03 00 00 00 04     SWIT(0): 00 00 00 04
0044-0045  05 00              Event counter ()
0048-....  06                 Unknown packet

Flush data SWOFlush

View terminal data

SWOView

 Receiving SWO data @ 6000 kHz.
Data from stimulus port 0:
-----------------------------------------------

Calibrate the target current measurement.

calibrate

Please disconnect emulator from target.
Press any key to start the calibration...

Calibrating...Emulator calibrated.
Min=-1mA Max=-1mA Avg=-1mA Offs=-1mA...DONE

Change endian mode le be little | big

Select a emulator to communicate selemu [Interface0 Interface1 ...]

list all emulators which are connected to the host.

ShowEmuList [Interface0 Interface1 ...]

J-Link[0]: Connection: USB, Serial number: 682930364, ProductName: J-Link OB-SAM3U128-V2-NordicSem

Set value for VTref VTREF ValuemV
15.4 Reference voltage (VTref)

log actions

This is usually only useful for the j-link development team

log filename

list license commands

license

license add   Store a custom license on J-Link. Syntax: LicAdd LicName
  license erase Erase all custom licenses on J-Link.
  license show  Show all licenses stored on J-Link.
J-Link>license show
Built-in licenses: 
No installable licenses.

Firmware info

f

Firmware: J-Link OB-SAM3U128-V2-NordicSemi compiled Jan 12 2018 16:05:20
Hardware: V1.00

Select device Device
Allows use of the J-Link flash programming as well as using unlimited breakpoints in flash memory.
mandatory For some devices to allow the DLL to perform special handling.

Select target interface. si SWD | JTAG | ICSP | FINE | …

Select SWD as interface and outputs the JTAG - SWD switching sequence. SWDSelect

current CPU state

IsHalted

        CPU is not halted.

Quit and Close connection qc

J-Link script files are written in C-like syntax

Script functions See section 7.13

`ConfigTargetSettings Before InitTarget`
`InitTarget`
`SetupTarget called after InitTarget`
`ResetTarget`
`InitEmu`

`OnTraceStart OnTraceStop`

`AfterResetTarget`
`SWO_EnableTarget SWO_GetSWOBaseClock`

`HandleBeforeFlashProg HandleAfterFlashProg`

`StartETM StopETM`	Embedded Trace Macrocell
`StartTPIU StopTPIU`	Trace Port Interface Unit
`StartTMC StopTMC`	Trace Memory Controller
`StartPTM StopPTM`	Program Flow Trace
`StartTF StopTF`	Trace Funnel
`StartETB StopETB`	Embedded Trace Buffer

J-Link Command Strings

see Section 7.14 or Segger

Use with exec

`AppendToLogFile`
`CORESIGHT_SetIndexAHBAP APBAP`
`CORESIGHT_SetETBBaseAddr, MTB, ETM, PTM, CSTF TMC or TPIU`
`CORESIGHT_SetTFEnableMask`

`device`

`DisableAutoUpdateFW`
`Ena/DisableCortexMXPSRAutoCorrect- TBit`
`Ena/DisableFlashBPs`
`Ena/DisableFlashDL`
`Ena/DisableInfoWinFlashBPs`
`Ena/DisableInfoWinFlashDL`
`Ena/DisableLowPowerHandlingMode`

`Ena/DisableMOEHandling`	output of additional information about mode of entry in case the target CPU is halted / entered debug mode.

`DisablePowerSupplyOnClose`
`Ena/DisableAutoUpdateFW`

`EnableEraseAllFlashBanks`
`Enables/Disables`	always appending new loginfo to logfile. Disables auto-correction of XPSR T-bit for Cortex-M devices.
`EnableRemarks`	detailed output during CPU-detection / connection process.
`ExcludeFlashCacheRange`

`HideDeviceSelection dialog`

`HSSLogFile`
`InvalidateCache`	Invalidate flash ranges in flash cache, that are configured to be excluded from flash cache.
`InvalidateFW`
`map exclude`	Ignores all memory accesses to specified area.
`map illegal`	Marks a specified memory region as an illegal memory area. Memory accesses to this region are ignored.
`map indirectread`
`map ram`
`map region`	Specifies a memory region.
`map reset`	restores mapping

`MemPreserveOnReset`

`ProjectFile`
`ReadIntoTraceCache`
`RTTTelnetAllowNonLocalClient`	Allows non local clients to connect to RTT over Telnet.

`ScriptFile`

`SelectTraceSource`
`SetAllowStopMode 0\|1`
`SetAllowFlashCache 0\|1`	Enables/Disables flash cache usage. <<<<<++++++
`SetHostIF`
`SetAllowSimulation`
`SetBatchMode`
`SetCFIFlash`
`SetCheckModeAfterRead`	Enables/Disables CPSR check after read operations.
`SetCompareMode`
`SetCPUConnectIDCODE CPU IDCODE`	that is used to authenticate the debug probe, when connecting to the CPU.
`SetDbgPowerDownOnClose`	Used to power-down the debug unit of the target CPU when the debug session is closed.
`SetEnableMemCache`	<<<+++ Enables/Disables DLL internal memory caching mechanisms that improve performance
`SetETBIsPresent ETM`	Selects if the connected device has an ETB./ETM
`SetFlashDLNoRMWThreshold`	Specifies a threshold when writing to flash memory does not cause a read-modify-write operation.
`SetFlashDLThreshold`	Set minimum amount of data to be downloaded. Specifies a file or directory which should be used by the J-Link DLL to save the current configuration. Allows/Disallows usage of stop mode for RTT and memory accesses.
`SetIgnoreReadMemErrors`
`SetIgnoreWriteMemErrors`
`SetMonModeDebug`
`SetResetPulseLen`
`SetResetType`
`SetRestartOnClose`
`SetRTTAddr`
`SetRTTSearchRanges`
`SetRTTTelnetPort`
`SetRXIDCode`
`SetSysPowerDownOnIdle`
`SetVerifyDownload`
`SetWorkRAM`
`ShowControlPanel`
`SilentUpdateFW`
`SupplyPower`
`SupplyPowerDefault`
`SuppressControlPanel`
`SuppressInfoUpdateFW`
`SWOSetConversionMode`
`TraceFile`
`TraceSampleAdjust`

`SetAllowFlashCache = 0 \| 1`	Enabled by default.

Projectfile

exec ProjectFile Mycmds..jlink to save the current configuration.
Example contents:

[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1             exec setAllowCache = 0
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

Wish it had

Memory search,

logger

NRF_LOG_LEVEL NRF_LOG_DEFAULT_LEVEL NRF_LOG_[HEXDUMP_] ERROR | WARNING | INFO | RAW_INFO | DEBUG

printf-like, formatted string with up to seven arguments.

With HEXDUMP arg.2 is length.

Compiled only if NRF_LOG_LEVEL includes xxx
GETCHGAR (waits), FLOAT[_MARKER]

NRF_LOG_LEVEL

Add -M to LDFLAGS +=… to generate symbol map.

OverTheAir D FirmwareUpload
075B20

-> /Applications/SEGGER/JLink_V633a/JFlashLite.app
JFlashLite.app                      JFlashLite          
JFlashSPI          
JLinkExe          
JLinkGDBServer.app                  JLinkGDBServer   
JLinkGDBServerCL  
JLinkLicenseManager.app 
JLinkRegistration.app 
JLinkRemoteServer.app               JLinkRemoteServer   
JLinkRemoteServerCLExe 
JLinkRTTClient      
JLinkRTTLogger      
JLinkSTM32         
JLinkSWOViewer    
JTAGLoadExe      
nrfjprog            -> /usr/local/Caskroom/nordic-nrf5x-command-line-tools/53406.17.93573317/nrfjprog/nrfjprog
mergehex            -> /usr/local/Caskroom/nordic-nrf5x-command-line-tools/53406.17.93573317/mergehex/mergehex
gcc-arm-none-eabi-4_9-2015q3-20150921-mac.tar
gcc-arm-none-eabi-4_9-2015q3/

Sample startup


4/28/19 JLink_MacOSX_V645d.pkg (finder  control click to open)

/Applications/SEGGER/JLink/JLinkExe #      s swd ; Speed
SEGGER J-Link Commander V6.45d (Compiled Apr  5 2019 17:04:01)
DLL version V6.45d, compiled Apr  5 2019 17:03:50

Connecting to J-Link via USB...O.K.
Firmware: J-Link OB-SAM3U128-V2-NordicSemi compiled Jan  7 2019 14:07:15
Hardware version: V1.00
S/N: 682394615
VTref=3.300V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. : NRF52832_XXAA
Type '?' for selection dialog
Device>
Please specify target interface:
  J) JTAG (Default)
  S) SWD
  T) cJTAG
TIF>s
Specify target interface speed [kHz]. : 4000 kHz
Speed>
Device "NRF52832_XXAA" selected.


Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
Found SW-DP with ID 0x2BA01477
Scanning AP map to find all available APs
AP[2]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
AP[1]: JTAG-AP (IDR: 0x02880000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
Cortex-M4 identified.

Errors

Connecting to J-Link via USB...FAILED: Cannot connect to J-Link via USB.

Is Nordic Dev board switched on?

Try another cable in case the USB is not a "power-only" (i.e. no-data) cable.

File is of unknown / supported format.
The file extension should be .hex or

Unspecified error -1 Check the cable.

Failed to open file.
The file may have a checksum err or or other format problem.

The connected J-Link (S/N xxxxxxxxx) is low on memory

WDOG notes

Segger download current MacOS package

Segger User Manual UM08001_JLink.pdf

Intel HEX format

Nordic Semiconductor nrfjprog Command Line interface to J-Link.

Not to be confused with /usr/bin/jlink which is part of the Sun (now oracale) java system!