Reset Reason
J-Link 

14 UICR - User information configuration registers

mem 10001080,80

10001080  UICR CUSTOMER[0]

100010FC  UICR CUSTOMER[31]



13 FICR - Factory information configuration registers Page 43
mem 10000000,120 10000000 = AA 55 AA 55 AA 55 AA 55 FF FF FF FF FF FF FF FF CODEPAGESIZE 010 Code memory page size 10000010 = 00 10 00 00 CODESIZE 014 Code memory size 80 00 00 00 18 ... 5F not defined in Product Spec FE FF FF FF FF FF FF FF 10000050 = FF FF FF FF FF FF FF FF 00 00 00 00 C7 00 FF FF DEVICEID used for Ruuvixxx not MAC 10000060 = 24 19 63 DA B6 6D E9 EF 68 ... 7F not defined in Product Spec FF FF FF FF FF FF FF FF 10000070 = 50 41 42 54 39 36 06 3E 55 FF FF FF FF FF FF FF [0] [1] ER Encryption Root 10000080 = 47 3F 09 4F EF 23 D3 FA E1 13 A1 3C 6D 03 0C 41 [0] [1] [2] [3] IR Identity Root 10000090 = E1 93 D0 FC D5 EF 33 57 69 F4 10 21 BB 91 87 0A DEVICEADDRTYPE 100000A0 = FF FF FF FF DEVICEADDR (lsb 0:public;1:random) mem 100000A4,6 C2 24 68 3C 10 87 MAC in reverse order this example apears as C7:10:3C:68:24:C2 when ruuviboot last digit is 3
AC ... FF not defined in Product Spec 00 00 00 00 00 00 00 00 00 00 00 00 INFO.PART 10000100 = 32 28 05 00 i.e. 53228 INFO.VARIANT 30 42 41 41 AAB0 INFO.PACKAGE 00 20 00 00 QFxx- 48 pin IINFO.RAM 40 00 00 00 64 KB RAM INFO.FLASH 10000110 = 00 02 512KB flash 00 00

10000120 FF FF FF FF 10000130 FF FF FF FF (checked by nrfjprog:nRF52_read_device_version 10000134 FF FF FF FF (checked by nrfjprog:nRF52_read_device_version FF FF FF FF …


10000240 = 87 59 AB 9C DD 56 9F 57 FF FF 11 32 C2 A9 CC FF 10000250 = 07 00 40 B8 80 FF FB FF FF FF FF FF FF FF FF FF 10000280 = AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 10000300 = FF FF FF FF FF FF FF FF 10 18 FF FF 06 10 FF FF 10000310 = 3A 48 FF FF 10 18 FF FF 06 10 FF FF FF FF FF FF 10000320 = F2 C2 C0 C2 FF F4 FF FF FF FF FF FF FF FF FF FF
> mem 10000400,60 TEMP.A0 slope definition 10000400 = FF FF FF FF 20 F3 FF FF 43 F3 FF FF 5D F3 FF FF ... [0] [1] [2] [3] A5 10000410 = 00 F4 FF FF 52 F4 FF FF 7B F3 FF FF y-intercept B0 CC 3F FF FF y-intercept B1 10000420 = 98 3F FF FF 98 3F FF FF 12 00 FF FF 4D 00 FF FF ... B5 10000430 = 10 3E FF FF TEMP.T0 E2 FF FF FF 00 FF FF FF 14 FF FF FF 10000440 = 19 FF FF FF 50 FF FF FF FF FF FF FF FF FF FF FF NFC.TAGHEADER0 10000450 = 5F 9D 89 47 45 F1 03 70 5A 9C 07 92 D0 55 D0 9B 10000A00 = AA 55 AA 55 FF FF FF FF FF FF FF FF FF FF FF FF
mem 10001010,70 10001010 = FF FF FF FF reserved 10001014 00 50 07 00 UICR NRFFW[0] firmware 10001018 00 E0 07 00 UICR NRFFW[1] 1000101C FF FF FF FF UICR NRFFW[2] … 1000107C FF FF FF FF UICR NRFFW[14] 10001050 FF FF FF FF UICR NRFHW[0] hardware … 1000107C FF FF FF FF UICR NRFHW[11] mem32 10001080,20 10001080 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF UICR CUSTOMER[0], 1, 2, 3 10001090 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 4 5, 6, 7 100010A0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 8 9,10,11 100010B0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 12, 13,14,15 100010C0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 16, 13,14,15 100010D0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 20, 13,14,15 100010E0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 24, 13,14,15 100010F0 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 28, 29,30,31
10001200 = 15 00 00 00 PSELRESET[0] reset pin mapping 15 00 00 00 PSELRESET[1] reset pin mapping Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. 1 before an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN 2 return to normal (read only) with CONFIG.REN 0 11.3 User Information Configuration Registers (UICR) are written in the same way as Flash. new UICR configuration will only take effect after a reset. Whoa! only write a 0; twrite 338us, writable 181 times then erase is required 11.4 ERASEUICR After erasing UICR all bits in UICR are set to '1'. Terase 89.7ms, Teraseall 295.3ms nRF5_SDK_12/components/device/nrf52.h typedef struct { /*!< FICR Structure __I uint32_t reserved0[4]; __I uint32_t CODEPAGESIZE; /*!< Code memory page size __I uint32_t CODESIZE; /*!< Code memory size __I uint32_t reserved1[18]; __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier __I uint32_t reserved2[6]; __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 __I uint32_t DEVICEADDRTYPE; /*!< Device address type __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 __I uint32_t reserved3[21]; FICR_INFO_Type INFO; /*!< Device info __I uint32_t reserved4[185]; FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients __I uint32_t reserved5[2]; FICR_NFC_Type NFC; /*!< Unspecified } NRF_FICR_Type; typedef struct { /*!< UICR Structure __IO uint32_t unused0; __IO uint32_t unused1; __IO uint32_t unused2; __I uint32_t reserved0; __IO uint32_t unused3; __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design __IO uint32_t NRFHW[12]; /*!< hardware design __IO uint32_t CUSTOMER[32]; /*!< customer __I uint32_t reserved1[64]; __IO uint32_t PSELRESET[2]; /*!< Mapping of the nRESET function __IO uint32_t APPROTECT; /*!< Access port protection __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna or GPIO __I uint32_t reserved2[60]; __IO uint32_t EXTSUPPLY; /*!< Enable external circuitry to be supplied from VDD pin. Applicable in 'High voltage mode' only. __IO uint32_t REGOUT0; /*!< GPIO reference voltage / external output supply voltage in 'High voltage mode'. } NRF_UICR_Type; * @brief Non Volatile Memory Controller (NVMC) */ typedef struct { /*!< NVMC Structure __I uint32_t reserved0[256]; __I uint32_t READY; /*!< Ready flag __I uint32_t reserved1[64]; __IO uint32_t CONFIG; /*!< Configuration register union { __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area }; __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers __I uint32_t reserved2[10]; __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. __I uint32_t reserved3; __IO uint32_t IHIT; /*!< I-Code cache hit counter. __IO uint32_t IMISS; /*!< I-Code cache miss counter. } NRF_NVMC_Type;

RESETREAS Reset Reason 18.9.3

RAM[0].POWER

mem32 40000400,1

00001Reset Pin
00002watchdog
00004soft reset SREQ
00008CPU lock-up Example:hardfault within the hardfault handler
wakeups from System OFF triggered from
10000 DETECT signal from GPIO
20000ANADETECT signal from LPCOMP
40000entering into debug interface mode
80000NFC field
cumulative. A field is cleared by writing '1' to it.
If none of the reset sources are flagged, a power-on-reset or a brownout reset.


System Hangs

See regs
PC = 00031A06, CycleCnt = 00000000
R0 = 00030276, R1 = 00030221, R2 = 0001F000, R3 = 00031A07
R4 = 200033CF, R5 = 200051DC, R6 = 200033C4, R7 = 200051E8
R8 = 00000000, R9 = 200051E0, R10= 200051E4, R11= 200051EA
R12= 2000FEE8
SP(R13)= 2000FF70, MSP= 2000FF70, PSP= 00000000, R14(LR) = FFFFFFF9
XPSR = 21000003: APSR = nzCvq, EPSR = 01000000, IPSR = 003 (HardFaultMemManage)
See load map for locations of fault: grep -i 00031A06 *.map

All fault _Handlers: NMI, HardFault, MemoryManagement, BusFault, UsageFault, SVC, DebugMon, PendSV, SysTick
are assigned to unique locations BUT all have B B B (FE E7) hangs!

All _IRQHandlers: QDEC, FPU, RADIO, UARTE0_UART0, I2S, SWI4_EGU4, PWM2, ECB, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, Default_Handler, CCM_AAR, PWM1, SWI5_EGU5, PWM0, SWI3_EGU3, SWI1_EGU1, SPIM2_SPIS2_SPI2, MWU, RTC0, PDM, COMP_LPCOMP, TEMP, All
are at the SAME location which contains B B B (FE E7) hangs!


Reset_Handler is:

319DC = 06 49 07 4A 07 4B 9B 1A 03 DD 04 3B C8 58 D0 50 
319EC = FB DC 00 F0 13 F8 ED F7 25 FD 00 00 F0 62 03 00 
319FC = 38 2C 00 20 A8 2F 00 20 
319DC:  06 49              LDR       R1, [PC, #+0x18]   //  __etext __exidx_end
319DE:  07 4A              LDR       R2, [PC, #+0x1C]   //  __data_start__
319E0:  07 4B              LDR       R3, [PC, #+0x1C]   //  __bss_start__

                                              R1=362F0, R2=20002C38, R3=20002FA8

319E2:  9B 1A              SUBS      R3, R3, R2         //   370
319E4:  03 DD              BLE       L1  #+0x06

319E6:  04 3B   L1         SUBS      R3, #4
319E8:  C8 58              LDR       R0, [R1, R3]    // copy __exidx_end
319EA:  D0 50              STR       R0, [R2, R3]    // to  __data_start__ 
319EC:  FB DC              BGT       L1  #-0x0A

319EE:  00 F0 13 F8        BL        SystemInit #+0x26

31A18:  30 B4 SystemInit   PUSH      {R4-R5}
31A1A:  A2 4B              LDR       R3, [PC, #+0x288]


Stack

mem 2000FF60,A0 2000FF60 = 93 00 00 20 00 00 00 00 CF 33 00 20 DC 51 00 20 2000FF70 = CF 33 00 20 08 00 00 00 3C 33 00 20 69 02 03 00 2000FF80 = E8 FE 00 20 21 02 03 00 76 02 03 00 00 00 00 61 2000FF90 = EC 51 00 20 21 02 03 00 01 00 00 00 00 00 00 50 2000FFA0 = 00 00 08 00 00 00 02 00 A1 2D 00 20 32 46 00 20 2000FFB0 = C2 24 68 3C 00 00 00 20 00 00 00 00 8B 4B 02 00 2000FFC0 = D8 FF 00 20 D3 FF 00 20 DC FF 00 20 74 ED 76 96 2000FFD0 = 55 18 99 2E 02 00 00 00 02 00 00 00 04 00 00 00 2000FFE0 = 00 00 00 00 00 00 00 00 00 00 00 00 68 3B 00 20 2000FFF0 = 00 00 00 00 00 00 00 00 00 00 00 00 8F F4 01 00